1. Field of the Invention
The present invention relates to a complementary semiconductor device and a method for producing the same. More particularly, the present invention relates to a complementary semiconductor device and a method for producing the same, by which a highly reliable high-speed semiconductor integrated circuit which can be operated with low power consumption can be provided while realizing a fine metal-oxide-semiconductor (MOS) type semiconductor device.
2. Description of the Related Art
The entire disclosure of U.S. patent application Ser. No. 08/879,579 filed Jun. 20, 1997 is expressly incorporated by reference herein.
Recently, in order to realize a very large-scale integrated circuit (VLSI) having even higher integration, the size of a MOS type semiconductor device usable for such a VLSI has been reduced even more in recent years. As a result, currently available semiconductor devices are formed with a minimum size in a half-micron region or in a sub-half micron region. At this stage of development, attempts have been made to produce a prototype semiconductor having a size on the order of a quarter micron or a subquarter micron.
However, if a device having such a small size is formed, the electric characteristics of the device are likely to be degraded because of a short-channel effect or a hot-carrier effect, thereby seriously influencing the reliability of the device.
On the other hand, in order to develop VLSI technologies satisfactorily applicable in the expanding multi-media society, a semiconductor device must realize not only high-speed operation but also low power consumption.
In order to improve the resistance of a device to the degradation caused by a hot-carrier effect or a short-channel effect, and to improve the drivability thereof, a MOS type semiconductor device having an asymmetric impurity concentration profile in the channel has been proposed. Such a MOS semiconductor device is described, for example, by T. Matsui et al. in 1991 Symposium on VLSI Technology, pp. 113-114, in which a laterally-doped channel (LDC) structure is proposed.
FIG. 1 is a cross-sectional view showing a MOS type semiconductor device 50 having an LDC structure.
The semiconductor device 50 includes: an n-type high-concentration source diffusion layer 2 and an n-type high-concentration drain diffusion layer 3, which are formed in a semiconductor substrate 1; a gate oxide film 4 formed on the semiconductor substrate 1; a gate electrode 5 formed on the gate oxide film 4; and a p-type high-concentration diffusion layer 6' provided in a channel region between the source diffusion layer 2 and the drain diffusion layer 3 and under the source diffusion layer 2 in the semiconductor substrate 1. The p-type diffusion layer 6' is characterized in that the impurity concentration thereof monotonically decreases from the source side to the drain side.
In this structure, by setting the impurity concentration on the source side of the p-type diffusion layer 6' to be high, it is possible to improve the resistance of the device to the short-channel effect. In addition, by setting the impurity concentration on the drain side of the p-type diffusion layer 6' to be low, it is possible to reduce a high electric field generated in the vicinity of the drain, thereby suppressing the generation of hot carriers. Therefore, a conventional lightly-doped drain (LDD) structure is not required for this semiconductor device 50, thereby realizing high drivability.
However, this structure is not suitable for a MOS type semiconductor device to be formed in a region having a size on the order of a quarter micron or less. This is because, the MOS type semiconductor device 50 having the LDC structure shown in FIG. 1 has the following problems.
Firstly, a p-type high-concentration diffusion layer is provided under a source diffusion layer and the impurity concentration in the p-type diffusion layer is as high as 1.times.10.sup.18 cm.sup.-3 or more in order to suppress the short-channel effect. As a result, the parasitic capacitance of the p-n junction between the source and the substrate is adversely increased as compared with a conventional structure.
In general, the speed of a MOS type semiconductor device (the speed as a whole circuit) is proportional to the product obtained by multiplying together the inverse of a saturated current value and a load capacitance. Therefore, if such a semiconductor device having a large parasitic capacitance in the p-n junction between the source and the substrate, as in the case of a semiconductor device 50 shown in FIG. 1 having an LDC structure, is applied to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device (the speed as a whole circuit) is adversely decreased.
On the other hand, the power consumed by a MOS type semiconductor device is proportional to the product obtained by multiplying together the load capacitance and the square of the applied voltage. Therefore, if a large parasitic capacitance exists in the p-n junction between the source and the substrate, the power consumption of the circuit is adversely increased.
Secondly, when a device having a size on the order of a quarter micron or less is formed, the threshold voltage is decreased and the device becomes seriously affected by the short-channel effect. The short-channel effect depends upon an effective channel length and a junction depth between the source diffusion layer and the drain diffusion layer. Since an LDC structure has a deep junction depth between the source diffusion layer and the drain diffusion layer, the decrease in the threshold voltage cannot be suppressed in a region having a size on the order of a quarter micron or less.
According to the conventional technologies of forming a MOS type semiconductor device, because of the above-described reasons, a highly reliable high-speed semiconductor device cannot be formed in a region having a size on the order of a quarter micron or less.